APM32F103TBU6-R datasheet(45/78 Pages) GEEHY

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P a g e 44

Symbo

Parameter

Condition

Minimum

value

Maximum

value

Unit

current at the same time

2.7V < VDD < 3.6V

VOH(2)

Output high level when 8 pins output

current at the same time

VDD-0.4

VOL(1)

Output low level when 8 pins absorbs

current at the same time

CMOS port, IIO = +8mA

2.7V < VDD < 3.6V

0.4

VOH(2)

Output high level when 8 pins output

current at the same time

2.4

VOL(1)(3)

Output low level when 8 pins absorbs

current at the same time

IIO = +20mA

2.7V < VDD < 3.6V

1.3

VOH(2)(3)

Output high level when 8 pins output

current at the same time

VDD-1.3(4)

The current IIO absorbed by I/O must always comply with the absolute maximum rated value

requirements, and the sum of IIO (all I/O and control pins) cannot exceed IVSS.

The current IIO outputted by I/O must always comply with the absolute maximum rated value

requirements, and the sum of I IO (all I/O and control pins) cannot exceed IVDD.

The data are obtained from a comprehensive evaluation and are not tested in production.

The drive capability of PC13-15 is not included in this item. The specification of other PC ports is

3.3V<VDD<3.6V within the voltage range.

5.10

NRST pin characteristics

The NRST pin input drive adopts CMOS process, and is connected with a permanent pull-up

resistor RPU.

Table36 NRST Pin Characteristics (TA=-40~105℃, VDD=3.3V)

Symbol

Parameter

Condition

Minimum

value

Typical

value

Maximum

value

Unit

VIL(NRST)(1)

NRST low-level input voltage

-0.5

0.8

VIH(NRST)(1)

NRST high-level input voltage

VDD+0.5

Vhys(NRST)

NRST Schmitt trigger voltage

hysteresis

300

RPU

Weak pull-up equivalent

resistance (2)

VIN = VSS

kΩ

Guaranteed by design and not tested in production.

The pull-up resistor is realized by connecting a pure resistor in series with a turn-off PMOS/NMOS

switch. The resistance of this PMOS/NMOS switch is very small.

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