APM32F103TBU6-R datasheet(24/78 Pages) GEEHY

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P a g e 23

operations.

I/O pin turnover speed on the APB2 can reach 18MHz.

4.10

Communication peripherals

4.10.1 USART

Three USART communication interfaces are embedded. Among them, the USART1 interface

can support the communication rate of 4.5Mbit/s, and the other interfaces support the

communication rate of 2.25Mbit/s. It has hardware signal CTS and RTS, compatible with

ISO7816 smart card, supports IrDA SIR ENDEC transmission encoding and decoding, and

provides LIN master/slave mode.

4.10.2 I2C

I2C1/2 can work in multi-master mode or slave mode and support 7-bit and 10-bit addressing.

The protocol supports standard and fast modes. Built-in hardware CRC generator/calibrator.

DMA operation can be used and SMBus bus version 2.0/PMBus bus is supported.

4.10.3 SPI

Two SPI interfaces are embedded, supporting the chip to communicate with external devices

in half/full duplex serial mode. It can be configured as master mode or slave mode, with 8 or 16

bits per frame. The communication rate in full-duplex and half-duplex mode can be 18 Mbit/s.

All SPI interfaces support DMA operation.

4.10.4 QSPI

1 QSPI special communication interface is embedded, which can connect external flash

through single-line, double-line or four-line SPI mode, and support 8-bit, 16-bit and 32-bit

access. There are 8-byte transmit FIFO and 8-byte receive FIFO inside. DMA operation is

supported.

4.10.5 CAN

2 built-in CAN bus interfaces (CAN1 and CAN2 can be used at the same time), compatible with

2.0A and 2.0B (active) specifications, which can communicate at a rate of up to 1Mbit/s.

Support standard frame with 11-bit identifier and extended frame with 29-bit identifier, and

have 3 transmitting mailboxes and 2 receiving FIFO, and 14 3-level adjustable filters.

4.10.6 USBD

The product embeds USBD modules (USBD1 and USBD2) compatible with full-speed USBD

devices, which comply with the standard of full-speed USBD devices (12Mb/s), and the

endpoints can be configured by software, and have standby/wake-up functions. The dedicated

48MHz clock for USBD is directly generated by internal PLL. When using the USBD function,

the system clock can only be one of 48MHz, 72MHz and 96MHz, which can obtain 48MHz

required for USBD through 1 divided frequency, 1.5 fractional frequency, and 2 fractional

frequency respectively.

APM32F103TBU6-R 数据表(PDF) 24 Page - Geehy Semiconductor Co., Ltd.

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