APM32F103C8T6-R datasheet(15/78 Pages) GEEHY

15 / 78 page

w w w. g e e h y. c o m

P a g e 14

Pin Name

Pin No.

Type

(1)

Main function (3)

Optional multiplexing function

(After reset)

Default

multiplexing

function

Redefining

function

PB3

I/O

JTDO

PB3/

TRACESWO/

TMR2_CH2/

SPI1_SCK

PB4

I/O

NJTRST

PB4/

TMR3_CH1/

SPI1_MISO

PB5

I/O

PB5

I2C1_SMBAI

TMR3_CH2/

SPI1_MOSI/

CAN2_RX

PB6

I/O

PB6

I2C1_SCL(6)/

TMR4_CH1(6)

USART1_TX/

CAN2_TX

PB7

I/O

PB7

I2C1_SDA(6)/

TMR4_CH2(6)

USART1_RX

BOOT0

PB8

I/O

PB8

TMR4_CH3(6)

I2C1_SCL/

/CAN1_RX

PB9

I/O

PB9

TMR4_CH4(6)

I2C1_SDA

/CAN1_TX

PE0

I/O

PE0

TMR4_ETR

PE1

I/O

PE1

VSS_3

VDD_3

100

VDD_3

Power supply capacity of PC13, PC14 and PC15 pins is weak. Therefore, there are the following

restrictions on these three pins: only one pin can be used as an output at the same time, and can

only work in 2MHz mode, the maximum driving load is 30pF, and they cannot be used as a current

source (such as driving LED).

The status of these pins is controlled by the backup area registers (these registers will not be

reset by the main reset system).

For Pin 2 and Pin 3 of QFN36 package, and Pin 5 and Pin 6 of LQFP48 and LQFP64 package, the

default configuration after the chip is reset is OSC_IN and OSC_OUT function pins, and the

software can reset these two pins with PD0 and PD1 functions; for LQFP100 package, PD0 and

PD1 are inherent function pins.

This multiplexing function can be configured to other pins by software (if the corresponding

package model has this pin). For details, please refer to the multiplexing function I/O section and

debugging setting section of the user manual.

APM32F103C8T6-R 数据表(PDF) 15 Page - Geehy Semiconductor Co., Ltd.

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