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APM32F103C8T6-R 数据表(PDF) 37 Page - Geehy Semiconductor Co., Ltd.

部件名 APM32F103C8T6-R
功能描述  Arm® Cortex® -M3 based 32-bit MCU
PDF  78 Pages
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制造商  GEEHY [Geehy Semiconductor Co., Ltd.]
网页  https://global.geehy.com/
标志 GEEHY - Geehy Semiconductor Co., Ltd.

APM32F103C8T6-R 数据表(HTML) 37 Page - Geehy Semiconductor Co., Ltd.

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P a g e 36
Symbol
Parameter
Condition
Minimum
value
Typical
value
Maximum
value
Unit
PLS[2:0]=011 (rising edge)
2.47
2.51
2.54
V
PLS[2:0]=011 (falling edge)
2.37
2.40
2.46
V
VPVD(3)
Programmable power
supply voltage
detector voltage level
selection
PLS[2:0]=100 (rising edge)
2.57
2.60
2.63
V
PLS[2:0]=100 (falling edge)
2.46
2.50
2.58
V
PLS[2:0]=101 (rising edge)
2.66
2.71
2.74
V
PLS[2:0]=101 (falling edge)
2.56
2.61
2.69
V
PLS[2:0]=110 (rising edge)
2.77
2.81
2.86
V
PLS[2:0]=110 (falling edge)
2.65
2.70
2.8
V
PLS[2:0]=111 (rising edge)
2.86
2.91
2.92
V
PLS[2:0]=111 (falling edge)
2.76
2.80
2.83
V
VPVDhyst(2)
PVD hysteresis
-
-
107
-
mV
VPOR/PDR
Power-on/power-down
reset threshold
Falling edge
1.86(1)
1.87
1.88
V
Rising edge
1.92
1.94
1.96
V
VPDRhyst (2)
PDR hysteresis
-
-
50
-
mV
TRSTTEMPO
Reset duration
-
0.9
-
2.4
ms
1.
The characteristics of the product are guaranteed by design to the minimum value VPOR/PDR.
2.
Guaranteed by design and not tested in production.
3.
The data are obtained from a comprehensive evaluation and are not tested in production.
5.7
Power Consumption
5.7.1
Power consumption test environment
The values are measured by executing Dhrystone 2.1, with the Keil.V5 compilation environment
and the L3 compilation optimization level.
All I/O pins are in analog input mode and are connected to a static level at VDD or VSS (no load)
Unless otherwise specified, all peripherals are disabled
The relationship between Flash wait cycle setting and fHCLK:
0~24MHz: 0 wait cycle
24~48MHz: 1 wait cycle
48~72MHz: 2 wait cycles
72~96MHz: 3 wait cycles
The instruction prefetch function is enabled (note: it must be set before clock setting and bus
frequency division)
When the peripherals are enabled: fPCLK1=fHCLK/2, fPCLK2 =fHCLK



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