AS1163 datasheet(37/91 Pages) AMSOSRAM

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AS1163

Functional description

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DS001075 • v2-00 • 2025-Nov-21

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When only 1 SPI port is used, the MCU needs to toggle the SPI role between sender and

receiver after a message has been sent and before the response is received. SAIDs apply a

wait time of min. 5 µs between the end of an incoming telegram and the start of a response

that is sent back to the sender. The clock phase on SIOx_N is selectable through register

settings, using the COM_INV bit in the SETUP register.

The figure below illustrates the signals for the SPI Type B MCU mode (pull-up on SIO_P and

pull-down on SIO_N and the two possible clock polarities, respectively.

Figure 19: SPI mode

Information:

SPI is only supported on SIO1 port.

6.5.7.1

SCK interruptions in SPI mode

An internal counter operating at the system clock is reset periodically at every edge of the

external clock (reconstructed clock in case of a Manchester signal).

The internal counter flags a communication error, 8 system clock cycles after the last clock

edge.

For example:

•

Nominal system clock of 19.2 MHz resulting in a period of about 52 ns.

•

The timeout is flagged after 8 system clock cycles, or 416 ns.

•

SCK interruptions can be tolerated if below 416 ns. Otherwise, a communication error is

detected and communication fails to receive the message.

AS1163 数据表(PDF) 37 Page - ams-OSRAM AG