AS1163 datasheet(18/91 Pages) AMSOSRAM

18 / 91 page

AS1163

Electrical characteristics

Datasheet • PUBLIC • Document Feedback

DS001075 • v2-00 • 2025-Nov-21

18 / 91

5.1

Power supply

For operating SAID a voltage supply VDD of typical 5 V is required. Each SAID can sink up to

nominal 288 mA from the LEDs and the power delivery network needs to be sized accordingly.

Decoupling caps are recommended between VDD and GND, placed as close as possible to

the device power pins.

Recommended values for these caps are:

•

1 μF elco capacity

•

100 nF high ESR capacitor

•

VDD voltage up to 6 V

5.2

Startup sequence

The device starts-up with VDD overcoming the UVLO (undervoltage lockout) threshold. After

the bandgap reference starts-up, the voltage regulator generates an internal voltage, VREG.

The internal blocks supplied by VREG (nominally 1.5 V) are reset until the supply reaches the

POR_N threshold. The RC oscillator is also enabled with POR_N. In this state, for a trimmed

device, the OTP is downloaded, and the trimming/configuration bits activated (~200 µs).

All internal blocks supplied by the external VDD supply start up after the supply reaches the

UVLO threshold. At this point the communication interface and the led drivers are functional.

Once the communication is enabled, also in case of an under-voltage event, the device does

not lose functionality until an internal falling POR_N event. The VDD_OK flag signals that the

VDD is above the VDD_UV threshold.

Note: VREG, POR_N are internal signals. At startup the current is increased up to 6mA to

ensure stable readout from the OTP for proper operation.

Figure 7: Startup sequence

AS1163 数据表(PDF) 18 Page - ams-OSRAM AG