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AS7341

Datasheet

• PUBLIC

DS000504

• v3-00 • 2020-Jun-25

│ 37

10.2.3

ADC Configuration (gai

n, AGC…)

The following registers provide configuration for the 6 integrated ADCs (CH0 to CH5). It is possible to

adjust the gain, configure and enable the automatic gain control (AGC) and setup the auto zero

compensation for the engines.

CFG1 Register (Address 0xAA)

Figure 49:

CFG1 Register

Addr: 0xAA

CFG1

Bit

Bit Name

Default

Access

Bit Description

7:5

reserved

4:0

AGAIN

Spectral engines gain setting.

Sets the spectral sensitivity.

VALUE

GAIN

0.5x

16x

32x

64x

128x

256x

512x

CFG10 Register (Address 0xB3)

Figure 50:

CFG10 Register

Addr: 0xB3

CFG10

Bit

Bit Name

Default

Access

Bit Description

7:6

AGC_H

AGC High Hysteresis.

Sets the data threshold at which AGAIN is reduced

when spectral AGC mode is enabled. The threshold

is automatically calculated internally as a percentage

of full-scale. Note that full-scale is equal to (ATIME +

1) x (ASTEP + 1).

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