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AS7341

Datasheet

• PUBLIC

DS000504

• v3-00 • 2020-Jun-25

│ 40

CFG8 Register (Address 0xB1)

Figure 53:

CFG8 Register

Addr: 0xB1

CFG8

Bit

Bit Name

Default

Access

Bit Description

7:6

FIFO_TH

R/W

FIFO Threshold.

Sets a threshold on the FIFO level that triggers the

first FIFO buffer interrupt (FINT).

VALUE

FIFO_LVL

5:4

reserved

FD_AGC

Flicker Detect AGC Enable.

If set, device uses automatic gain control for the

flicker detect engine to maximize flicker signal and

avoid saturation.

SP_AGC

Spectral AGC enable.

If asserted, device uses automatic gain control for

the spectral engines to maximize signal while

avoiding saturation.

reserved

10.2.4

Device Identification

The following registers provided device identification. Device ID, revision ID and auxiliary ID are read

only.

AUXID Register (Address 0x90)

Figure 54:

AUXID Register

Addr: 0x90

AUXID

Bit

Bit Name

Default

Access

Bit Description

7:4

reserved

3:0

AUXID

000

Auxiliary identification

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