AS7341 datasheet(50/69 Pages) AMSOSRAM

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AS7341

Datasheet

• PUBLIC

DS000504

• v3-00 • 2020-Jun-25

│ 49

10.2.7

Spectral Data and Status

The ASTATUS register is mapped to register address 0x60 and 0x94. It provides saturation and gain

status associated to each set of spectral data. Reading the ASTATUS register (0x60 or 0x94) latches

all 12 spectral data bytes to that status read. Reading these bytes consecutively (0x60 to 0x6F or 0x94

to 0xA0) ensures that the data is concurrent. All spectral data are stored as 16-bit values. If flicker

detection is enabled, spectral channel five (CH5 ADC) is used for the flicker detection function and

CH5_DATA

will read “0”. The ASTATUS and spectral data registers are read only.

In SPM or SYNS mode, it is recommended to use the ASTATUS register 0x94 and spectral data

implementation.

ASTATUS Register (Address 0x60 or 0x94)

Figure 69:

ASTATUS Register

Addr: 0x60 and 0x94

ASTATUS

Bit

Bit Name

Default

Access

Bit Description

ASAT_STATUS

R, SC

Saturation Status.

Indicates if the latched data is affected by analog or

digital saturation.

6:4

reserved

3:0

AGAIN_STATUS

R, SC

Gain Status.

Indicates the gain applied for the spectral data

latched to this ASTATUS read. The gain from this

status read is required to calculate spectral results if

AGC is enabled.

CH0_DATA Register (Address 0x95/0x96)

Figure 70:

CH0_DATA_L Register

Addr: 0x95

CH0_DATA_L

Bit

Bit Name

Default

Access

Bit Description

7:0

CH0_DATA_L

CH0 ADC data

– low byte

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