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RZ/G2LC 数据表(PDF) 32 Page - Renesas Technology Corp |
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RZ/G2LC 数据表(HTML) 32 Page - Renesas Technology Corp |
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32 / 74 page  RZ/G2L Group, RZ/G2LC Group 3. Electrical Characteristics R01DS0484EJ0110 Rev.1.10 Page 32 of 74 May 30, 2025 3.5.3 eMMC Access Timing 3.5.3.1 eMMC Host Interface Timing (Default) Table 3.22 eMMC Host Interface Timing (MMC Default 3.3-V Power Supply) Item Symbol Min. Max. Unit Figures SD0_CLK clock cycle tMMCPP 40.00 — ns Figure 3.9 SD0_CLK clock high level width tMMCWH 18.50 — ns SD0_CLK clock low level width tMMCWL 18.50 — ns SD0_CLK clock rise time tMMCLH — 3 ns SD0_CLK clock fall time tMMCHL — 3 ns SD0_CMD/SDDAT output delay tMMCODLY −4.50 4.0 ns SD0_CMD/SDDAT input set up time tMMCISU 5.5 — ns SD0_CMD/SDDAT input hold time tMMCIH 2.0 — ns SD0_CMD/SDDAT input data width tMMCIDW — — ns Table 3.23 eMMC Host Interface Timing (MMC Default 1.8-V Power Supply) Item Symbol Min. Max. Unit Figures SD0_CLK clock cycle tMMCPP 40.00 — ns Figure 3.9 SD0_CLK clock high level width tMMCWH 19.25 — ns SD0_CLK clock low level width tMMCWL 19.25 — ns SD0_CLK clock rise time tMMCLH — 2.45 ns SD0_CLK clock fall time tMMCHL — 2.45 ns SD0_CMD/SDDAT output delay tMMCODLY −2.00 2.50 ns SD0_CMD/SDDAT input set up time tMMCISU 4.00 — ns SD0_CMD/SDDAT input hold time tMMCIH 1.40 — ns SD0_CMD/SDDAT input data width tMMCIDW — — ns |
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