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RZ/G2LC 数据表(PDF) 44 Page - Renesas Technology Corp

部件名 RZ/G2LC
功能描述  RZ 32 & 64-bit MPUs, RZ/G Series
PDF  74 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

RZ/G2LC 数据表(HTML) 44 Page - Renesas Technology Corp

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RZ/G2L Group, RZ/G2LC Group
3. Electrical Characteristics
R01DS0484EJ0110
Rev.1.10
Page 44 of 74
May 30, 2025
3.5.8
JTAG Debugger Interface Access Timing
Table 3.35
Debugger IF Timing
Item
Symbol
Min.
Max.
Unit
Figures
TCK_SWCLK cycle time
tTCKcyc
50
—
ns
Figure 3.23
TCK_SWCLK high pulse width
tTCKH
20
—
ns
Figure 3.24
TCK_SWCLK low pulse width
tTCKL
20
—
ns
TDI setup time
tTDIS
15
—
ns
TDI hold time
tTDIH
15
—
ns
TMS_SWDIO setup time
tTMSS
15
—
ns
TMS_SWDIO hold time
tTMSH
15
—
ns
SWDIO delay time
tSWDO
—
14
ns
TDO delay time
tTDOD
—
14
ns
Capture register setup time
tCAPTS
10
—
ns
Figure 3.25
Capture register hold time
tCAPTH
10
—
ns
Update register delay time
tUPDATED
—
20
ns
1/2 JTAG_PVDD
tTCKcyc
tTCKH
tTCKL
VIH
VIH
VIL
VIL
VIH
1/2 JTAG_PVDD
Figure 3.23
TCK_SWDCLK Input Timing



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