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RZ/G2LC 数据表(PDF) 46 Page - Renesas Technology Corp |
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RZ/G2LC 数据表(HTML) 46 Page - Renesas Technology Corp |
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46 / 74 page  RZ/G2L Group, RZ/G2LC Group 3. Electrical Characteristics R01DS0484EJ0110 Rev.1.10 Page 46 of 74 May 30, 2025 3.5.9 SPI Multi I/O Bus Controller Access Timing Table 3.36 SPI Multi I/O Bus Contoller Access Timing (1/2) 1.8 V 3.3 V (Serial flash/octal-SPI flash/hyper flash connected) (Serial flash connected) Item Symbol Min. Max. Min. Max. Unit Figures Clock cycle tSPBcyc 10.0 — 15.0 — ns Figure 3.26, Figure 3.30 CLK high pulse width tSPBWH 0.45 0.55 0.45 0.55 tSPBcyc Figure 3.26, Figure 3.30 CLK low pulse width tSPBWL 0.45 0.55 0.45 0.55 tSPBcyc Figure 3.26, Figure 3.30 CLK rise time tSPBR — 1.0 — 3.2 ns Figure 3.26, Figure 3.30 CLK fall time tSPBF — 1.0 — 3.2 ns Figure 3.26, Figure 3.30 Data input setup time QSPI0_SPCLK base point (SDR mode timing adjusted) tSU 6.7 — 7.5 — ns Figure 3.27 QSPI0_SPCLK base point (DDR mode timing adjusted) 4.5 — 4.5 — ns Figure 3.28 QSPI1_SSL base point (DQS base point) −0.9*2 — ― — ns Figure 3.31 Data input hold time QSPI0_SPCLK base point (SDR mode timing adjusted) tH 0.5 — 0.5 — ns Figure 3.27 QSPI0_SPCLK base point (DDR mode timing adjusted) 1.0 — 1.0 — ns Figure 3.28 QSPI1_SSL base point (DQS base point) 2.69*2 — — — ns Figure 3.31 SSL setup time tLEAD 1.5 × tSPBcyc − 3 8.5 × tSPBcyc + 3 1.5 × tSPBcyc − 3 8.5 × tSPBcyc + 3 ns Figure 3.27, Figure 3.28, Figure 3.31 SSL hold time tLAG 1 × tSPBcyc − 3 8 × tSPBcyc + 3 1 × tSPBcyc − 3 8 × tSPBcyc + 3 ns Figure 3.27, Figure 3.28, Figure 3.31 Continuous transfer delay time tTD 1 × tSPBcyc − 3 8 × tSPBcyc + 3 1 × tSPBcyc − 3 8 × tSPBcyc + 3 ns Figure 3.27, Figure 3.28, Figure 3.31 Data output delay time SDR tOD ― 2.0 ― 5.0 ns Figure 3.27 DDR ― 6.5*2 ― 7.5*3 ns Figure 3.28 Hyper/octal ― 2.8 ― ― ns Figure 3.31 Data output hold time SDR tOH −2.0 ― -5.0 ― ns Figure 3.27 DDR 1.0*2 ― 2.1*3 ― ns Figure 3.28 Hyper/octal 0.9 ― ― ― ns Figure 3.31 Skew of Clock to Data Strobe tCKDS ― 7.0 ― ― ns Figure 3.31 |
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