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MPC855T 数据表(PDF) 49 Page - Freescale Semiconductor, Inc |
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MPC855T 数据表(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 80 page  MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor 49 CPM Electrical Characteristics Figure 50. CPM General-Purpose Timers Timing Diagram 11.6 Serial Interface AC Electrical Specifications Table 19 provides the serial interface timings as shown in Figure 51 through Figure 55. Table 19. SI Timing Num Characteristic All Frequencies Unit Min Max 70 L1RCLK, L1TCLK frequency (DSC = 0)1, 2 — SYNCCLK/2.5 MHz 71 L1RCLK, L1TCLK width low (DSC = 0)2 P + 10 — ns 71a L1RCLK, L1TCLK width high (DSC = 0)3 P + 10 — ns 72 L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time — 15.00 ns 73 L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time) 20.00 — ns 74 L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time) 35.00 — ns 75 L1RSYNC, L1TSYNC rise/fall time — 15.00 ns 76 L1RXD valid to L1CLK edge (L1RXD setup time) 17.00 — ns 77 L1CLK edge to L1RXD invalid (L1RXD hold time) 13.00 — ns 78 L1CLK edge to L1ST(1–4) valid 4 10.00 45.00 ns 78A L1SYNC valid to L1ST(1–4) valid 10.00 45.00 ns 79 L1CLK edge to L1ST(1–4) invalid 10.00 45.00 ns 80 L1CLK edge to L1TXD valid 10.00 55.00 ns 80A L1TSYNC valid to L1TXD valid 4 10.00 55.00 ns 81 L1CLK edge to L1TXD high impedance 0.00 42.00 ns 82 L1RCLK, L1TCLK frequency (DSC =1 ) — 16.00 or SYNCCLK/2 MHz 83 L1RCLK, L1TCLK width low (DSC = 1) P + 10 — ns 83a L1RCLK, L1TCLK width high (DSC = 1)3 P + 10 — ns CLKO TIN/TGATE (Input) TOUT (Output) 64 65 61 62 63 61 60 |
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