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ST7LITE3XF2 数据表(PDF) 75 Page - STMicroelectronics |
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ST7LITE3XF2 数据表(HTML) 75 Page - STMicroelectronics |
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75 / 173 page  ST7LITE3xF2 75/173 LITE TIMER (Cont’d) 11.3.4 Low Power Modes 11.3.5 Interrupts Note: The TBxF and ICF interrupt events are con- nected to separate interrupt vectors (see Inter- rupts chapter). They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction). 11.3.6 Register Description LITE TIMER CONTROL/STATUS REGISTER 2 (LTCSR2) Read / Write Reset Value: 0x00 0000 (x0h) Bits 7:2 = Reserved, must be kept cleared. Bit 1 = TB2IE Timebase 2 Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled Bit 0 = TB2F Timebase 2 Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR2 register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred LITE TIMER AUTORELOAD REGISTER (LTARR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:0 = AR[7:0] Counter 2 Reload Value. These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. Mode Description SLOW No effect on Lite timer (this peripheral is driven directly by fOSC/32) WAIT No effect on Lite timer ACTIVE-HALT No effect on Lite timer HALT Lite timer stops counting Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Active Halt Exit from Halt Timebase 1 Event TB1F TB1IE Yes Yes No Timebase 2 Event TB2F TB2IE Yes No No IC Event ICF ICIE Yes No No 70 0 000 00 TB2IE TB2F 70 AR7 AR7 AR7 AR7 AR3 AR2 AR1 AR0 1 |
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