ST7LITE3XF2 datasheet(8/173 Pages) STMICROELECTRONICS

8 / 173 page

ST7LITE3xF2

8/173

Notes:

1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA

pins to ground.

2. For input with interrupt possibility “eix” defines the associated external interrupt vector which can be as-

signed to one of the I/O pins using the EISR register. Each interrupt can be either weak pull-up or floating

defined through option register OR.

PA6 /MCO/

ICCCLK/

BREAK

I/O

ei1

Port A6

Main Clock Output or In Circuit Com-

munication Clock or External BREAK

Caution: During normal operation this

pin must be pulled- up, internally or ex-

ternally (external pull-up of 10k manda-

tory in noisy environment). This is to

avoid entering ICC mode unexpectedly

during a reset. In the application, even

if the pin is configured as output, any re-

set will put it back in input pull-up.

PA5 /ATPWM3/

ICCDATA

I/O CT HS

Port A5

Auto-Reload Timer PWM3 or In Circuit

Communication Data

14 PA4/ATPWM2

I/O CT HS

Port A4

Auto-Reload Timer PWM2

15 PA3/ATPWM1

I/O CT HS

ei0

Port A3

Auto-Reload Timer PWM1

16 PA2/ATPWM0

I/O CT HS

Port A2

Auto-Reload Timer PWM0

17 PA1/ATIC

I/O CT HS

Port A1

Auto-Reload Timer Input Capture

18 PA0/LTIC

I/O CT HS

Port A0

Lite Timer Input Capture

19 OSC2

Resonator oscillator inverter output

20 OSC1/CLKIN

Resonator oscillator inverter input or External

clock input

Pin Name

Level

Port / Control

Main

Function

(after

reset)

Alternate Function

Input

Output

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