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ST7LITE3XF2 数据表(PDF) 103 Page - STMicroelectronics |
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ST7LITE3XF2 数据表(HTML) 103 Page - STMicroelectronics |
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103 / 173 page ![]() ST7LITE3xF2 103/173 LINSCI ™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) BAUD RATE REGISTER (SCIBRR) Read/Write Reset Value: 0000 0000 (00h) Note: When LIN slave mode is disabled, the SCI- BRR register controls the conventional baud rate generator. Bits 7:6 = SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conven- tional Baud Rate Generator mode. Bits 2:0 = SCR[2:0] SCI Receiver rate divider These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. 70 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 PR Prescaling factor SCP1 SCP0 1 0 0 31 4 1 0 13 1 TR dividing factor SCT2 SCT1 SCT0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1 RR dividing factor SCR2 SCR1 SCR0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1 |
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