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ST10R172LT6 数据表(PDF) 41 Page - STMicroelectronics |
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ST10R172LT6 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 68 page  41/68 ST10R172L - ELECTRICAL CHARACTERISTICS where N = number of consecutive TCLs and 1 ≤ N ≤ 40. So for a period of 3 TCLs (i.e. N = 3): and PLL jitter is an important factor for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Figure 12 Approximated maximum PLL jitter D 3 43 15 ⁄ – = 3,8% = 3TCL min 3TCL NOM 1 3,8 100 ⁄ – () × = 3TCL NOM 0,962 36.07nsec @fcpu=50MHz () × = 32 16 8 4 2 ±1 ±2 ±3 ±4 Max.jitter [%] N This formula is valid for 1<N<40 and 10<fcpu<50 1 |
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