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STR730FZ1T7 数据表(PDF) 50 Page - STMicroelectronics |
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STR730FZ1T7 数据表(HTML) 50 Page - STMicroelectronics |
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50 / 52 page ![]() Known limitations STR73xFxx 50/52 7 Known limitations 7.1 Low power wait for interrupt mode When the STR73x device is put in Low Power Wait For Interrupt mode (LPWFI), the Flash goes into low power mode or power down mode, depending on the setting of the PWD bit in the Flash Control Register 0 (default is ‘0’, Low Power mode). This default mode can create excessive voltage conditions on the transistor gates and may affect the long term behavior of the Low Power mode circuitry. Workaround There is no workaround. If Low Power Wait For Interrupt mode is used, it is strongly suggested to configure the Flash to enter power down mode (bit PWD = ‘1’). 7.2 PLL free running mode at high temperature When the STR73x device is operated and an ambient temperature (TA) of more than 55° C and the main system clock (fMCLK) is sourced by the PLL in free running mode, the device may not work properly. Workaround At high temperature (more than 55° C), it is recommended to use the internal RC oscillator as a backup clock source rather than the PLL free running mode. |
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