2/15

ST16-19RFRDCS

FSD_CHIPSET_B/0104VP2

1.2.2 Interface signals definition

The signals used for the interface between FPGA & MCU, in transmission and reception, are:

Mic_Data(7:0): Data bidirectional bus.

Mic_strb_b: FPGA strobe signal (Activ low) used to sample the data.

This signal is sent by the MCU to the FPGA

Mic_RW: Writing/Reading signal (’1’=reading, ’0’=writing).

This signal is sent by the MCU to the FPGA

Mic_Ctrl_Data: Registers/FIFOs access signal (’1’ = Register access, ’0’ = FIFOs access).

This signal is sent by the MCU to the FPGA

Tx_start: Transmission command, used to start data transmission from FIFO to output pin.

This signal is sent by the MCU to the FPGA

Tx_fifo_empty: Signal used to indicate transmission fifo empty.

This signal is sent by the FPGA to the MCU

Rx_fifo_empty: Signal used to indicate reception fifo empty.

This signal is sent by the FPGA to the MCU

Rx_irq_eof: IRQ reception end.

This signal is sent by the FPGA to the MCU

1.3 FIFOS ACCESS

1.3.1 Transmission FIFO (cf figure 1)

At the end of a transmission (or during power-on), the FPGA sets the transmission FIFO pointers to zero.

This way, Tx_Fifo_Empty is validated, and so the software has to check that transmission FIFO is empty

before sending a new frame.

1.3.2 Reception FIFO (cf figures 2 & 3)

The reading pointer of reception FIFO is reset after each new frame received. It is impossible to get more

than one frame in the FIFO. Thus, after each interruption, data stored in the FIFO has to be read until val-

idation of Rx_Fifo_Empty signal.

WARNINGS: - Reception FIFO reading is done in "lookahead" mode. Bytes are read by the FPGA

in internal mode before being read by the MCU. Thus, the Rx_Fifo_Empty signal is valid just before

reading the last byte in the FIFO. FIFO reception has to be read once more when Rx_Fifo_Empty is

valid to get the last byte of the received frame.