8/15

ST16-19RFRDCS

FSD_CHIPSET_B/0104VP2

1.6.2 Status register

The mapping of the different state bits is given by the following table:

Table 3 : Reception status register description

1.7 FPGA PIN-OUT & CHIP SET BLOCK DIAGRAM

The FPGA pin-out is given by the list below:

Table 4 : FPGA pin out

"Address

"Description

’0

Reception Control

bit [1:0]:

Rx_Speed_Value

"00" = 106K

"01" = 212K

"10" & "11"= 424K

bit 2:

Rx_CRC_OK

’0’ = CRC OK

’1’ = CRC Wrong

bit 3:

Rx_EGT_TooLong

‘0' = EGT OK

'1' = EGT too long

bit 4:

Rx_Bad_StopBit

‘0' = Stop Bit Value OK '1' = Stop Bit wrong => frame wrong?

bit 5:

ST Reserved => read at '0'

bit 6:

ST Reserved => read at '0'

bit 7:

ST Reserved => read at '0'

Signal

Site

clk1356

P2

mic_ctrl_ndata

P176

mic_data<0>

P184

mic_data<1>

P185

mic_data<2>

P186

mic_data<3>

P187

mic_data<4>

P188

mic_data<5>

P189

mic_data<6>

P190

mic_data<7>

P191

mic_r_nw

P181

mic_strb_b

P179

reset

P102

rx_bpsk_in

P48

rx_fifo_empty

P89

rx_irq_eof

P180

rx_valid

P198

tx_fifo_empty

P29

tx_start

P30

tx_streamout

P37