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FSD_CHIPSET_B/0104VP2

ST16-19RFRDCS

1.6 REGISTERS MAPPING

1.6.1 Control Registers

The control bits mapping is given by the following table:

Table 2 : Control register description

Example:

Register " Reception Control ": MSB

LSB

01000011

bit [7:6] "01": identification of the Register " Reception Control "

bit [5:4] "00": set to ’0’

bit [3:2] "00": speed 106K

bit 1

’1’ : automatic speed detection

bit 0

’1’ : external valid

“Address

"Description

"00”

Functionality Mode Setting

bit 0:

Cfg_Irq_Pulse

'0' = Toggle Mode

’1’ = Pulse Mode

bit 1:

Cfg_Irq_High

'0' = Pulse Activ Low

‘1' = Pulse Activ High

bit 2:

Cfg_Loopback

’0’ = Usual Functionality

‘1' = Loop back

bit 3:

ST Reserved => set to '0'

bit 4:

ST Reserved => set to '0

bit 5:

ST Reserved => set to '0'

bit [7:6]:

Register Address Bits => set to "00"

"01”

Reception Control

bit 0:

Rx_Valid_Ext

’0’ = Digital Detection

’1’ = External Valid

bit 1:

Rx_Speed_Auto

’0’ = By Rx_Speed_Config Bits

’1’ = Automatic

bit [3:2]:

Rx_Speed_Config

"00" = 106K

"01" = 212K

"10" & "11" = 424K

bit 4:

ST Reserved => set to ’0’

bit 5:

ST Reserved => set to ’0’

bit [7:6]:

Register Address Bits => set to "01"

"10”

Register 1 Transmission Control

bit [1:0]:

Tx_Speed_Config

"00" = 106K

"01" = 212K

"10" & "11" = 424K

bit[4:2]:

Tx_Egt_Config

Number of d’EGT bits

bit 5:

ST Reserved => set to ’0’

bit [7:6]:

Register Address Bits => set to "10"

“11”

Register 2 Transmission Control

bit 0:

Tx_CRC_Disable

'0' = CRC automatic

‘1' = CRC disable

bit 1:

Tx_SOF_0_11

'0' = SOF of 10 bits at ‘0’

’1' = SOF of 11 bits at ‘0’

bit 2:

Tx_SOF_1_3

'0' = SOF of 2 bits at '1'

'1' = SOF of 3 bits at '1'

bit 3:

Tx_EOF_0_11

'0' = EOF of 10 bits at '0'

'1' = EOF of 11 bits at '0'

bit 4:

ST Reserved => set to '0'

bit 5:

ST Reserved => set to '0'

bit [7:6]:

Register Address Bits => set to "11"