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FSD_CHIPSET_B/0104VP2

ST16-19RFRDCS

1.4 CONTROL REGISTERS

1.4.1 Reception control bits

Rx_Valid_Ext: Valid_Frame signal is provided by the Analog Front End or detected by the FPGA

(’1’= External Valid, ’0’= Digital Detection).

Rx_Speed_Auto: Reception Speed Detection (’1’= automatic, ’0’= by Rx_Speed_Low Bit).

Rx_Speed_Config: Reception Rate ("00"=106K, "01"=212K, "10"=424K, "11"=424K).

1.4.2 Transmission Control bits

Tx_Speed_Config: Transmission Rate ("00"=106K, "01"=212K, "10"=424K, "11"=424K).

Tx_Egt_Config: Number of ETU bits between data characters.

Tx_CRC_Disable: Allows to insert or not the two CRC bytes at the end of the frame

(’0’= CRC automatic, ’1’= CRC disable).

Tx_SOF_0_11: Number of ’0’s inside the Start Of Frame (’0’=10, ’1’=11).

Tx_SOF_1_3: Number of ’1’s inside the Start Of Frame (’0’=2, ’1’=3).

Tx_EOF_0_11: Number of ’0’s inside the End Of Frame (’0’=10, ’1’=11).

1.4.3 Others Control bits

Two bits control the functional mode and polarity of the interruption used to indicate the end of a received

frame.

Cfg_Irq_Pulse: IRQ Functionality (’0’=Toggle, ’1’=Pulse).

Cfg_Irq_High: Interrupt Pulse Polarity (’0’=Low, ’1’=High).

In order to be able to test the Card Reader functionality at power-on, it’s possible to connect the transmis-

sion on the reception inside the FPGA (Loop Mode).

Cfg_Loopback: Connection of the transmission on the reception. (’1’= Connection, ’0’= Normal Running)