L6591

Application information

19/32

Figure 12.

Operation after latched disable activation: timing diagram

This function is useful to implement a latched over temperature protection very easily by

biasing the pin with a divider from VREF, where the upper resistor is an NTC physically

located close to a heating element like the MOSFET, or the secondary diode or the

transformer. An OVP can be implemented as well, e.g. by sensing the output voltage and

transferring an overvoltage condition via an optocoupler.

5.6

Oscillator and dead-time programming

connected from pin OSC (#5) to VREF (#6) and to ground respectively. Once chosen the

oscillator frequency and the dead-time duration needed, the values of RT and CT can be

calculated as:

Equation 1

Equation 2

can be verified with good approximation using the following formula:

 

Vcc

LVG, H VG

Vin

t

t

t

t

4.5V

DIS

HV generator is turn ed on

PFC_STOP

Vcc

off

Vcc

Disable latch is reset here

HV gen erator tu rn-on is disabled here

Inpu t sou rce i s re moved he re

d

osc

T

10

125

T

f

1150

50

R

−

⋅

−

+

=

()

50

R

R

1200

R

f

1

39

.

1

C

T

T

T

osc

T

−

−

⋅

⋅

=