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ST486DX 数据表(PDF) 17 Page - STMicroelectronics |
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ST486DX 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 34 page ![]() Valid Cases P I I/O Write Data Size I/O Write Address I/O Write Data ESI or EDI not an I/O ins. x x x x x x IN 0 0 x x x EDI INS 0 0 x x x EDI REP INS 1 0 x x x EDI OUT al 0 1 01h I/O Address xxxxxxdd ESI OUT ax 0 1 03h I/O Address xxxxdddd ESI OUT eax 0 1 0Fh I/O Address dddddddd ESI OUTSB 0 1 01h I/O Address xxxxxxdd ESI OUTSW 0 1 03h I/O Address xxxxdddd ESI OUTSD 0 1 0Fh I/O Address dddddddd ESI REP OUTSB 1 1 01h I/O Address xxxxxxdd ESI REP OUTSW 1 1 03h I/O Address xxxxdddd ESI REP OUTSD 1 1 0Fh I/O Address dddddddd ESI Table 3 - 2 Valid I/O Trap Cases x: invalid CS SMM base specified by SMAR, CS limit is set to 4 GBytes EIP 0000 0000h; Begins execution at the base of SMM memory EFLAGS 0000 0002h; Reset State CR0 6000 0010h; Real Mode, Cache in Write Through DR7 0000 0400h; Traps disabled Table 3 - 3 SMM Entry State ST486DX - SMM SOFTWARE CONSIDERATIONS 27 The values found in the I/O trap information fields are specified below for all cases. Upon SMM entry, the CPU enters the following state: |
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