ST486DX - SMM SOFTWARE CONSIDERATIONS

33

; Set MMAC to access main memory

MMAC = 1 shl 3

mov

al, 0c1h

;select CCR1

out

22h, al

in

al, 23h

;get CCR1 current value

mov

ah, al

;save it

mov

al, 0c1h

;select CCR1 again

out

22h, al

mov

al, ah

or

al, MMAC

;set MMAC

out

23h, al

;write new value to CCR1

;Now all data memory access will use ADS#, Code fetches

;will continue to be done with SMADS# from SMM memory.

;

;Disable MMAC

mov

al, 0c1h

;select CCR1

out

22h, al

mov

al, ah

;get old value of CCR1

out

23h, al

;and restore it

3.6

I/O Restart

When implementing power management into a system it is common to want to power down periph-

erals when they are not in use. When an I/O instruction is issued to a powered down device, the

SMM routine is called to power up the peripheral and then reissue the I/O instruction. SGS-Thom-

son CPUs make it easy to restart the I/O instruction that has generated an SMI interrupt.

The system will generate an SMI interrupt when an I/O bus cycle to a powered-down peripheral is

detected. The SMM routine should interrogate the system hardware to find out if the SMI was

caused by an I/O trap. By checking the SMM header information, the SMM routine can determine

the type of I/O instruction that was trapped. If the I/O instruction has a REP prefix, the ECX regis-

ter needs to be incremented before restarting the instruction. If the I/O trap was on a string I/O in-

struction, the ESI or EDI registers must be restored to their previous value before restarting the

instruction.

The following code example shows how easy I/O restart is with the SGS Thomson CPU.

;Restart the interrupted instruction

mov

eax,dword ptr cs:[SMI_CURRENTIP]

mov

dword ptr cs:[SMI_NEXTIP],eax

mov

al,byte ptr cs:[SMI_BITS]

;test for REP instruction