ST486DX - SMM SOFTWARE CONSIDERATIONS

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3.3.2

Maintaining Control Registers

CR0 is maintained in the SMM header. CR2 and CR3 need only be saved if the SMM routine will

be entering protected mode and enabling paging. Most SMM routines will not need to enable pag-

ing. However, if the CPU is going to be powered off, these registers like all the others need to be

saved.

3.3.3

Maintaining Debug Registers

DR7 is maintained in the SMM Header. Since DR7 is automatically initialized to the reset state on

entry to SMM, the Global Disable bit (DR7 bit 13) will be cleared. This allows the SMM routine

to access all of the Debug Registers. Returning from the SMM handler will reload DR7 with its

previous value. In most cases, SMM routines will not make use of the Debug Registers and they

will only need to be saved if the CPU needs to be powered down.

3.3.4

Maintaining Configuration Control Registers

The SMM routine should be written so that it maintains the Configuration Control Registers in the

state that they were initialized to by the BIOS at power-up.

3.3.5

Maintaining FPU State

If power will be removed from the FPU, or if the SMM routine will execute FPU instructions, then

the FPU state needs to be maintained for the application running before SMM was entered. If the

FPU state is to be saved and restored from within SMM, there are certain guidelines that must be

followed to make SMM completely transparent to the application program.

The complete state of the FPU can be saved and restored with the FNSAVE and FNRSTOR instruc-

tions. FNSAVE is used instead of the FSAVE because FSAVE will wait for the FPU to check for

existing error conditions before storing the FPU state. If there is a unmasked FPU exception condi-

tion pending, the FSAVE instruction will wait until the exception condition is serviced. In order to

be transparent to the application program, the SMM routine should not service the exception. If the

FPU state is restored with the FNRSTOR instruction before returning to normal mode, the applica-

tion program can correctly service the exception. Any FPU instructions can be executed within

SMM once the FPU state has been saved.

The information saved with the FSAVE instruction varies depending on the operating mode of the

CPU. To save and restore all FPU information, the 32-bit protected mode version of the FPU save