ST63156 datasheet(12/86 Pages) STMICROELECTRONICS

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ST631xx CORE (Continued)

Indirect Registers (X, Y). These two indirect reg-

isters are used as pointers to the memory locations

in the data space. They are used in the register-in-

direct addressing mode.These registers can be

addressed in the data space as RAM locations at

the 80h (X) and 81h (Y) addresses. They can also

be accessed with the direct, short direct, or bit di-

rect addressing modes. Accordingly, the ST631xx

instruction set can use the indirect registers as any

other register of the data space.

Short Direct Registers (V, W). These two regis-

ters are used to save one byte in short direct ad-

dressing mode. These registers can be addressed

in the data space as RAM locations at the 82h (V)

and 83H (W) addresses. They can also be ac-

cessed with the direct and bit direct addressing

modes. Accordingly, the ST631xx instruction set

can use the short direct registers as any other reg-

ister of the data space.

Program Counter (PC)

The program counter is a 12-bit register that con-

tains the address of the next ROM location to be

processed by the core. This ROM location may be

an opcode, an operand, or an address of operand.

The 12-bit length allows the direct addressing of

4096 bytes in the program space. Nevertheless, if

the program space contains more than 4096 loca-

tions, the further program space can be addressed

by using the Program ROM Page Register. The PC

value is incremented, after it is read for the address

of the current instruction, by sending it through the

ALU, so giving the address of the next byte in the

program. To execute relative jumps the PC and the

offset values are shifted through the ALU, where

they will be added, and the result is shifted back

into the PC. The program counter can be changed

in the following ways:

JP (Jump) instruction.... PC = Jump address

CALL instruction ........... PC= Call address

Relative Branch

instructions ................... PC= PC+offset

Interrupt........................ PC= Interrupt vector

Reset ............................ PC= Reset vector

RET & RETI instructions............ PC=Pop (stack)

Normal instruction ........ PC = PC+1

Flags (C, Z)

The ST631xx Core includes three pairs of flags

that correspond to 3 different modes: normal

mode, interrupt mode and Non-Maskable-Inter-

rupt-Mode. Each pair consists of a CARRY flag

and a ZERO flag. One pair (CN, ZN) is used during

normal operation, one pair is used during the inter-

rupt mode (CI,ZI) and one is used during the not-

maskable interrupt mode (CNMI, ZNMI).

The ST631xx Core uses the pair of flags that corre-

sponds to the actual mode: as soon as an interrupt

(resp. a Non-Maskable-Interrupt) is generated, the

ST631xx Core uses the interrupt flags (resp. the

NMI flags) instead of the normal flags. When the

RETI instruction is executed, the normal flags

(resp. the interrupt flags) are restored if the MCU

was in the normal mode (resp. in the interrupt

mode) before the interrupt. Should be observed

that each flag set can only be addressed in its own

routine (Not-maskable interrupt, normal interrupt

or main routine). The interrupt flags are not cleared

during the context switching and so, they remain in

the state they were at the exit of the last routine

switching.

The Carry flag is set when a carry or a borrow oc-

curs during arithmetic operations, otherwise it is

cleared. The Carry flag is also set to the value of

the bit tested in a bit test instruction, and partici-

pates in the rotate left instruction.

The Zero flag is set if the result of the last arithmetic

or logical operation was equal to zero, otherwise it

is cleared.

The switching between these three sets is auto-

matically performed when an NMI, an interrupt and

a RETI instructions occur. As the NMI mode is

automatically selected after the reset of the MCU,

the ST631xx Core uses at first the NMI flags.

ST63140,142,126,156

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