ST63156 datasheet(21/86 Pages) STMICROELECTRONICS

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Interrupt Vectors/Sources

The ST631xx Core includes 5 different interrupt

vectors in order to branch to 5 different interrupt

routines. The interrupt vectors are located in the

fixed (or static) page of the Program Space.

The interrupt vector associated with the non-mask-

able interrupt source is named interrupt vector #0.

It is located at addresses FFCh,FFDh in the Pro-

gram Space. This vector is associated with the

PC6/IRIN pin.

The interrupt vectors located at addresses

(FF6h,FF7h),

(FF4h,FF5h),

(FF2h,FF3h),

(FF0h,FF1h) are named interrupt vectors #1, #2,

#3 and #4 respectively. These vectors are associ-

ated with TIMER 2 (#4), VSYNC (#2), and TIMER

1 (#3). Interrupt vector (#1) is not used on

ST631xx.

Interrupt Priority

The non-maskable interrupt request has the high-

est priority and can interrupt any other interrupt

routines at any time, nevertheless the other inter-

rupts cannot interrupt each other. If more than one

interrupt request is pending, they are processed by

the ST631xx Core according to their priority level:

vector #1 has the higher priority while vector #4 the

lower. The priority of each interrupt source is hard-

ware fixed.

Interrupt Option Register

The Interrupt Option Register (IOR register, loca-

tion C8h) is used to enable/disable the individual

interrupt sources and to select the operating mode

of the external interrupt inputs. This register can be

addressed in the Data Space as RAM location at

the C8h address, nevertheless it is write-only reg-

ister that can not be accessed with single-bit op-

erations. The operating modes of the external

interrupt inputs associated to interrupt vectors #1

and #2 are selected through bits 5 and 6 of the IOR

Interrupt

Source

Associated

Vector

Vector Address

IRIN/NMI

(1)

Interrupt

Vector # 0 (NMI)

0FFCh-0FFDh

None

(2)

Interrupt

Vector # 1

0FF6h-0FF7h

Vsync

Interrupt

Vector # 2

0FF4h-0FF5h

Timer 1

Interrupt

Vector # 3

0FF2h-0FF3h

Timer 2

Interrupt

Vector # 4

0FF0h-0FF1h

Notes:

1. This pin is associated with the NMI Interrupt Vector

2. This vector is not used in ST631xx.

Table 6. Interrupt Vectors/Sources Relationships

INTERRUPT (Continued)

IOR

Interr upt Option Register

(C8h, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Unuse d

GEN = Global Enab le Bit

ES2 = Edge Selection Bit

EL1 = Edge Level Selection Bit

Unuse d

Figure 18. Interrupt Option Register

D7. Not used.

EL1. This is the Edge/Level selection bit of inter-

rupt #1. When set to one, the interrupt is generated

on low level of the related signal; when cleared to

zero, the interrupt is generated on falling edge. The

bit is cleared to zero after reset and as no interrupt

source is associated to vector #1 on ST631xx, the

user must keep this bit at zero to avoid ghost inter-

rupts from this source.

ES2. This is the edge selection bit on interrupt #2.

This bit is used on the ST631xx devices with on-

chip OSD generator for VSYNC detection.

GEN. This is the global enable bit. When set to one

all interrupts are globally enabled; when this bit is

cleared to zero all interrupts are disabled (EXclud-

ing NMI).

D3 - D0. These bits are not used.

ST63140,142,126,156

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