ST63156 datasheet(37/86 Pages) STMICROELECTRONICS

37 / 86 page

During transmission or reception of data, all ac-

cess to serial data register is therefore disabled.

The reception or transmission of data is started by

setting the BUSY bit to “1”; this will be automat-

ically reset at the end of the operation. After reset,

the busy bit is cleared to “0”, and the hardware SPI

disabled by clearing bit 0 and bit 1 of SPI control

SPI are “ANDed” to the standard I/O software con-

trolled outputs. If the hardware SPI is in operation

the Port C pins related to the SPI should be config-

ured as outputs using the Data Direction Register

and should be set high. When the SPI is configured

as the S-BUS, the three pins PC0, PC1 and PC3

become the pins SCL, SDA and SEN respectively.

When configured as the I

2CBUS the pins PC0 and

PC1 are configured as the pins SCL and SDA; PC3

is not driven and can be used as a general purpose

I/O pin. In the case of the STD SPI the pins PC0

and PC1 become the signals CLOCK and DATA,

PC3 is not driven and can be used as general pur-

pose I/O pin. The VERIFY bit is available when the

SPI is configured as either S-BUS or I

2CBUS. At

the start of a byte transmission, the verify bit is set

to one. If at any time during the transmission of the

following eight bits, the data on the SDA line does

not match the data forced by the SPI (while SCL is

high), then the VERIFY bit is reset. The verify is

available only during transmission for the S-BUS

and I

2CBUS; for other protocol it is not defined.

The SDA and SCL signal entering the SPI are buff-

ered in order to remove any minor glitches. When

STD bit is set to one (S-BUS or I

2CBUS selected),

and TRX bit is reset (receiving data), and STOP bit

is set (last byte of current communication), the SPI

interface does not generate the Acknowledge, ac-

cording to S-BUS/I

2CBUS specifications. PCO-

SCL, PC1-SDA and PC3-SEN lines are standard

drive I/O port pins with open-drain output configura-

tion (maximum voltage that can be applied to these

pins is VDD+0.3V).

S-BUS/I

2CBUS Protocol Information

The S-BUS is a three-wire bidirectional data-bus

with functional features similar to the I

2CBUS. In

fact the S-BUS includes decoding of Start/Stop

conditions and the arbitration procedure in case of

multimaster system configuration (the ST631xx

SPI allows a single-master only operation). The

SDA line, in the I

2CBUS represents the AND com-

bination of SDA and SEN lines in the S-BUS. If the

SDA and the SEN lines are short-circuit con-

nected, they appear as the SDA line of the

2CBUS. The Start/Stop conditions are detected (by

the external peripherals suited to work with S-

BUS/I

2CBUS) in the following way:

- On S-BUS by a transition of the SEN line (1 to 0

Start, 0 to 1 Stop) while the SCL line is at high

level.

- On I

2CBUS by a transition of the SDA line (10

Start, 01Stop) while the SCL line is at high

level.

Start and Stop condition are always generated by

the master (ST631xx SPI can only work as single

master). The bus is busy after the start condition and

can be considered again free only when a certain

time delay is left after the stop condition. In the S-

BUS configuration the SDA line is only allowed to

change during the time SCL line is low. After the start

information the SEN line returns to high level and re-

mains unchangedfor all the data transmission time.

When the transmission is completed the SDA line is

set to high level and, at the same time, the SEN line

returns to the low level in order to supply the stop in-

formation with a low to high transition, while the SCL

line is at high level. On the S-BUS, as on the I

2CBUS,

each eight bit information (byte) is followed by one

acknowledged bit which is a high level put on the

SDA line by the transmitter. A peripheral that ac-

knowledges has to pull down the SDA line during the

acknowledge clock pulse. An addressed receiver

has to generate an acknowledge after the reception

of each byte; otherwise the SDA line remains at the

high level during the ninth clock pulse time. In this

case the master transmitter can generate the Stop

condition, via the SEN (or SDA in I

2CBUS) line, in

order to abort the transfer.

SERIAL PERIPHERAL INTERFACE (Continued)

ST63140,142,126,156

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