ST72141K datasheet(111/132 Pages) STMICROELECTRONICS

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ST72141K

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8-BIT A/D CONVERTER (ADC) (Cont’d)

8.5.6 Register Description

CONTROL/STATUS REGISTER (CSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = COCO

Conversion Complete

This bit is set by hardware. It is cleared by soft-

ware reading the result in the DR register or writing

to the CSR register.

0: Conversion is not complete.

1: Conversion can be read from the DR register.

Bit 6 = Reserved. Must always be cleared.

Bit 5 = ADON

A/D converter On

This bit is set and cleared by software.

0: A/D converter is switched off.

1: A/D converter is switched on.

Note: A typical 30 µs delay time is necessary for

the ADC to stabilize when the ADON bit is set.

Bit 4 = Reserved. Forced by hardware to 0.

Bit 3 = Reserved. Must always be cleared.

Bits 2:0: CH[2:0]

Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

Table 44. Channel Selection

*IMPORTANT NOTE: The number of pins AND

the channel selection vary according to the device.

REFER TO THE DEVICE PINOUT).

DATA REGISTER (DR)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:0 = AD[7:0]

Analog Converted Value

This register contains the converted analog value

in the range 00h to FFh.

Reading this register resets the COCO flag.

Table 45. ADC Register Map and Reset Values

COCO

ADON

CH2

CH1

CH0

Pin*

CH2

CH1

CH0

AIN0

000

AIN1

001

AIN2

010

AIN3

011

AIN4

100

AIN5

101

AIN6

110

AIN7

111

AD7AD6

AD5AD4

AD3AD2

AD1

AD0

Address

(Hex.)

Label

7654

3210

0070h

ADCDR

Reset Value

IS11

IS10

MCO

IS21

IS20

CP1

CP0

SMS

0071h

ADCCSR

Standard

Reset Value

COCO

ADON

CH2

CH1

CH0

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