ST72C254G2 datasheet(74/135 Pages) STMICROELECTRONICS

74 / 135 page

ST72104G, ST72215G, ST72216G, ST72254G

74/135

I2C BUS INTERFACE (Cont’d)

Acknowledge may be enabled and disabled by

software.

The I

2C interface address and/or general call ad-

dress can be selected by software.

The speed of the I

2C interface may be selected

between Standard (0-100KHz) and Fast I2C (100-

400KHz).

SDA/SCL Line Control

Transmitter mode: the interface holds the clock

line low before transmission to wait for the micro-

controller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line

low after reception to wait for the microcontroller to

read the byte in the Data Register.

The SCL frequency (Fscl) is controlled by a pro-

grammable clock divider which depends on the

I2C bus mode.

When the I2C cell is enabled, the SDA and SCL

ports must be configured as floating inputs. In this

case, the value of the external pull-up resistor

used depends on the application.

When the I2C cell is disabled, the SDA and SCL

ports revert to being standard I/ O port pins.

Figure 44. I2C Interface Block Diagram

DATA REGIS TER (DR)

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTE R 1 (OAR1)

CLOCK CONTR OL REGISTER (CCR)

STATUS REGISTER 1 (SR1)

CONTROL REGISTER (CR)

CONTROL LOGIC

STATUS REGISTER 2 (SR2)

INTE RRUPT

CLOCK CONTR OL

DATA CONTROL

SCL or SCLI

SDA or SDAI

OWN ADDRESS REGISTER 2 (OAR2)

ST72C254G2 数据表(PDF) 74 Page - STMicroelectronics

ST72C254G2 数据表(HTML) 74 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载