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ST72C254G2 数据表(PDF) 20 Page - STMicroelectronics

部件名 ST72C254G2
功能描述  8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, I2C INTERFACES
PDF  135 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST72C254G2 数据表(HTML) 20 Page - STMicroelectronics

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RESET SEQUENCE MANAGER (Cont’d)
6.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 12).
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
6.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
s
Power-On RESET
s
Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 12.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
6.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 12.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 12. RESET Sequences
VDD
RUN
RESET PIN
EXTERNAL
WATCHDOG
DELAY
VIT+
VIT-
th(RSTL)in
tw(RSTL)out
RUN
DELAY
th(RSTL)in
DELAY
WATCHDOG UNDERFLOW
tw(RSTL)out
RUN
RUN
DELAY
RUN
RESET
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (4096 TCPU)
FETCH VECTOR



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