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ST7LITE05 数据表(PDF) 103 Page - STMicroelectronics |
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ST7LITE05 数据表(HTML) 103 Page - STMicroelectronics |
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103 / 122 page ![]() ST7LITE0, ST7SUPERLITE 103/122 ADC CHARACTERISTICS (Cont’d) 13.11.0.1 General PCB Design Guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. – Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital out- puts on the same I/O port as the A/D input being converted. ADC Accuracy TA = -40°C to 85°C, unless otherwise specified Notes: 1) Data based on characterization results over the whole temperature range, monitored in production. 2) Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 13.8 does not affect the ADC accuracy. Symbol Parameter Conditions Typ Max Unit ET Total unadjusted error 2) fCPU=4MHz, fADC=2MHz ,VDD=5.0V ±1 LSB EO Offset error 2) -0.5 / +1 EG Gain Error 2) ±1 ED Differential linearity error 2) ±11) EL Integral linearity error 2) ±11) ET Total unadjusted error 2) fCPU=8MHz, fADC=4MHz ,VDD=5.0V ±2 LSB EO Offset error 2) -0.5 / 3.5 EG Gain Error 2) -2 / 0 ED Differential linearity error 2) ±11) EL Integral linearity error 2) ±11) |
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