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STA308

3.2.2 DDX Compensating Pulse Size Register

3.2.3 High-Pass Filter Bypass

The STA308 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter

is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage

3.3 Configuration Register D (address 03h)

3.3.1 Binary Output Enable Registers

Each two-channel pair of outputs can be set to output a binary PWM stream. In this mode, output A

of a channel will be considered the positive output and output B is negative inverse. For example, setting C34BO

= 1 sets channels 3&4 to Binary Output (PWM) Mode.

3.3.2 Clock Output Select

BIT

R/W

RST

NAME

DESCRIPTION

2

R/W

1

CSZ0

Contra Size Register : When OM(1,0) = 11, this register determines the

size of the DDX compensating pulse from 0 clock ticks to 31 clock periods.

3

R/W

1

CSZ1

4

R/W

1

CSZ2

5

R/W

1

CSZ3

6

R/W

1

CSZ4

CSZ(4..0)

Compensating Pulse Size

00000

0 Clock period Compensating Pulse Size

00001

1 Clock period Compensating Pulse Size

……

11111

31 Clock period Compensating Pulse Size

BIT

R/W

RST

NAME

DESCRIPTION

7

R/W

0

HPB

High-Pass Filter Bypass Bit. Setting of one bypasses internal AC

coupling digital high-pass filter

BIT

D7

D6

D5

D4

D3

D2

D1

D0

NAME

BQL

PSL

COS1

COS0

C78BO

C56BO

C34BO

C12BO

RST

00

1

0

0

0

0

0

BIT

R/W

RST

NAME

DESCRIPTION

0

R/W

0

C12BO

Channels 1&2, 3&4, 5&6, 7&8 Binary Output Mode Enable

Bits. A setting of 0 indicates ordinary DDX tri-state output. A

setting of 1 indicates binary output mode.

1

R/W

0

C34BO

2

R/W

0

C56BO

3

R/W

0

C78BO

BIT

R/W

RST

NAME

DESCRIPTION

4

R/W

0

COS0

Clock Output Select

5

R/W

1

COS1

Clock Output Select