AD7264

Rev. A | Page 17 of 32

TYPICAL CONNECTION DIAGRAMS

Figure 26 and Figure 27 are typical connection diagrams for the

AD7264. In these configurations, the AGND pin is connected

to the analog ground plane of the system, and the DGND pin is

connected to the digital ground plane of the system. The analog

inputs on the AD7264 are true differential and have an input

impedance in excess of 1 GΩ; thus, no driving op amps are

required. The AD7264 can operate with either an internal or an

external reference. In Figure 26, the AD7264 is configured to

operate in control register mode; thus, G0 to G3, PD1, and PD2

can be connected to ground (low logic state). Figure 27 has the

gain pins configured for a gain of 2 setup; thus, the device is in

pin driven mode. Both circuit configurations illustrate the use

of the internal 2.5 V reference.

a 5 V supply. All supplies should be decoupled with a 100 nF

capacitor at the device pin, and some supply sources may

require a 10 μF capacitor where the source is supplied to the

3 V or 5 V.

100nF

3V OR 5V

SUPPLY

MICROPROCESSOR/

MICROCONTROLLER

COMPARATOR

100nF

100nF

100nF

ANALOG

SUPPLY

+5V

100nF

100nF

100nF

100nF

G0

G1

G2

G3

SCLK

REFSEL

CAL

PD1

PD2

13 14 15 16

45 46 47 48

25 26 29 30

22

23

36

24

32

35

34

37

38

39

40

27

31

21

3.125V

CONNECT

DIRECTLY

TO SENSOR

OUTPUTS

THIS REFERENCE SIGNAL

MUST BE BUFFERED

BEFORE IT CAN BE

USED ELSEWHERE IN

THE CIRCUIT

2.500V

1.875V

GAIN 2

3.125V

2.500V

1.875V

GAIN 2

3.125V

2.500V

1.875V

GAIN 2

3.125V

2.500V

1.875V

GAIN 2

CONNECT

DIRECTLY

TO SENSOR

OUTPUTS

1µF

1µF

17 44 5 6 8 19 42 28 2 7 11 20 41 12 1 33

10

9

18

43

4

3

AD7264

FAST PROPAGATION DELAY

COMPARATOR INPUTS

LOW POWER

COMPARATOR INPUTS

SERIAL

INTERFACE

CS

Figure 26. Typical Connection Diagram for the AD7264 in Control Register Mode (All Gain Pins Tied to Ground) Configured for a PGA Gain of 2