AD7264BSTZ datasheet(25/32 Pages) AD

25 / 32 page

AD7264

Rev. A | Page 25 of 32

CALIBRATION

The AD7264 registers store the offset value, which can easily be

accessed by the user (see the Reading from a Register section).

When the device is calibrating, the differential analog inputs

for each respective ADC are shorted together internally and a

conversion is performed. A digital code representing the offset is

stored internally in the offset registers, and subsequent conver-

sion results have this measured offset removed.

INTERNAL OFFSET CALIBRATION

The AD7264 allows the user to calibrate the offset of the device

using the CAL pin. This is achieved by setting the CAL pin to a

high logic level, which initiates a calibration on the next CS

falling edge. The calibration requires one full conversion cycle,

which contains a CS falling edge followed by 19 SCLK cycles.

The CAL pin can remain high for more than one conversion, if

desired, and the AD7264 continues to calibrate.

When the AD7264 is calibrated, the calibration results stored in

the internal device registers are relevant only for the particular

PGA gain selected at the time of calibration. If the PGA gain is

changed, the AD7264 must be recalibrated. If the device is not

recalibrated when the PGA gain is changed, the offset for the

previous gain setting continues to be removed from the digital

output code, which may lead to inaccuracies.

The CAL pin should be driven high only when the CS pin is

high or after 19 SCLK cycles have elapsed when CS is low, that

is, between conversions. The CAL pin must be driven high t12

before CS goes low. If the CS pin goes low before t12 elapses, the

calibration result will be inaccurate for the current conversion;

if the CAL pin remains high, the subsequent calibration conver-

sion is correct. If the CAL pin is set to a logic high state during a

conversion, that conversion result is corrupted.

The offset range that can be calibrated for is ±500 LSB at a gain

of 1. The maximum offset voltage that can be calibrated for is

reduced as the gain of the PGA is increased.

If the CAL pin has been held high for a minimum of one

conversion and when t12 and t11 have been adhered to, the

calibration is complete after the 19th SCLK cycle and the CAL

pin can be driven to a logic low state. The next CS falling edge

after the CAL pin has been driven to a low logic state initiates

a conversion of the differential analog input signal for both

ADC A and ADC B.

Table 12 details the maximum offset voltage that can be

removed by the AD7264 without compromising the available

digital output code range. The least significant bit size is

AVCC/2Bits, which is 5/16,384 or 305 μV for the AD7264. The

maximum removable offset voltage is given by

Gain

μV

305

LSB

500

Table 12. Offset Voltage Range

Alternatively, the control register can be used to initiate an

offset calibration. This is done by setting the CAL bit in the

control register to 1. The calibration is then initiated on the next

CS falling edge, but the current conversion is corrupted. The

ADCs on the AD7264 must remain fully powered up to

complete the internal calibration.

Gain

Maximum Removable Offset Voltage

±152.5 mV

±76.25 mV

±50.83 mV

±4.765 mV

SCLK

CAL

t12

t11

Figure 36. Calibration Timing Diagram

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