AD7264BSTZ datasheet(23/32 Pages) AD

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AD7264

Rev. A | Page 23 of 32

SERIAL INTERFACE

Figure 33 and Figure 34 show the detailed timing diagrams for

the serial interface on the AD7264. The serial clock provides the

conversion clock and controls the transfer of information from

the AD7264 after the conversion. The AD7264 has two output

pins corresponding to each ADC. Data can be read from the

AD7264 using both DOUTA and DOUTB. Alternatively, a single

output pin of the user’s choice can be used. The SCLK input

signal provides the clock source for the serial interface.

The falling edge of CS puts the track-and-hold into hold mode,

at which point the analog input is sampled. The conversion is

also initiated at this point and requires a minimum of 19 SCLK

cycles to complete. The DOUTx lines remain in three-state while

the conversion is taking place. On the 19th SCLK falling edge, the

AD7264 returns to track mode and the DOUTA and DOUTB lines

are enabled. The data stream consists of 14 bits of data, MSB first.

The MSB of the conversion result is clocked out on the 19th

SCLK falling edge to be read by the microcontroller or DSP on

the subsequent SCLK falling edge (the 20th falling edge). The

remaining data is then clocked out by subsequent SCLK falling

edges. Thus, the 20th falling clock edge on the serial clock has

the MSB provided and also clocks out the second data bit. The

remainder of the 14-bit result follows, with the final bit in the

data transfer being valid for reading on the 33rd falling edge.

The LSB is provided on the 32nd falling clock edge.

The AD7264-5, with its 20 MHz SCLK frequency, easily

facilitates reading on the SCLK falling edge. When using a

VDRIVE voltage of 5 V with the AD7264, the maximum specified

access time (t4) is 23 ns, which enables reading on the subse-

quent falling SCLK edge after the data has been clocked out, as

described previously. However, if a VDRIVE voltage of 3 V is used

for the AD7264 and the setup time of the microcontroller or

DSP is too large to enable reading on the falling SCLK edge, it

may be necessary to read on the SCLK rising edge. In this case,

the MSB of the conversion result is clocked out on the 19th SCLK

falling edge to be read on the 20th SCLK rising edge, as shown in

Figure 35. This is possible because the hold time (t5) is longer for

lower VDRIVE voltages. If the data access time is too long to accom-

modate the setup time of the chosen processor, an alternative to

reading on the rising SCLK edge is to use a slower SCLK frequency.

On the rising edge of CS, DOUTA and DOUTB go back into three-

state. If CS is not brought high after 33 SCLK cycles but is instead

held low for an additional 14 SCLK cycles, the data from ADC B

is output on DOUTA after the ADC A result. Likewise, the data

from ADC A is output on DOUTB after the ADC B result. This is

illustrated in

, which shows the DOUTA example. In this

case, the DOUT line in use goes back into three-state on the 47th

SCLK falling edge or the rising edge of

Figure 34

CS, whichever occurs first.

If the falling edge of SCLK coincides with the falling edge of CS,

the falling edge of SCLK is not acknowledged by the AD7264,

and the next falling edge of SCLK is the first one registered after

the falling edge of CS.

SCLK

DOUTA

THREE-STATE

THREE-

STATE

DB11A

DB12A

DB13A

DB1A

DB0A

DOUTB

THREE-STATE

THREE-

STATE

DB11B

DB12B

DB13B

DB1B

DB0B

tQUIET

FIRST DATA BIT CLOCKED

OUT ON THIS EDGE

FIRST DATA BIT READ

ON THIS EDGE

Figure 33. Normal Mode Operation

DOUTA

THREE-STATE

THREE-

STATE

SCLK

DB13A

DB12A

DB1A

DB0A

DB13B

DB12B

DB1B

DB0B

t10

Figure 34. Reading Data from Both ADCs on One DOUT Line with 47 SCLK Cycles

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