AD7264

Rev. A | Page 21 of 32

Power-Up Conditions

On power-up, the status of the gain pins determines which

mode of operation is selected, as outlined in the Gain Selection

section. All registers are set to 0.

If the AD7264 is powered up in pin driven mode, the gain pins

and the PD pins should be configured to the appropriate logic

states and a calibration initiated if required.

Alternatively, if the AD7264 is powered up in control register

mode, the comparators and ADCs are powered down and the

default gain is 1. Thus, powering up in control register mode

requires a write to the device to power up the comparators and

the ADCs.

It takes the AD7264 15 μs to power up when using an external

reference. When the internal reference is used, 240 μs are required

to power up the AD7264 with a 1 μF decoupling capacitor.

CONTROL REGISTER

The control register on the AD7264 is a 12-bit read and write

register that is used to control the device when not in pin driven

AD7264 when the gain pins are set to 0 (that is, the part is not in

pin driven mode). The control register can be used to select the

gain of the PGAs, the power-down modes, and the calibration

of the offset for both ADC A and ADC B. When in the control

register mode of operation, PD1 and PD2 should be connected

to a low logic state. These functions can also be implemented by

setting the logic levels on the gain pins, power-down pins, and

CAL pin, respectively. The control register can also be used to

read the offset and gain registers.

falling edge of SCLK when CS is in a logic low state. The control

register is selected by first writing the appropriate four WR bits,

as outlined in

. The 12 data bits must then be clocked

SCLK edge, the LSB is clocked into the device. One more SCLK

cycle is then required to write to the internal device registers. In

total, 17 SCLK cycles are required to successfully write to the

conversion result is being processed. The data transferred on

next conversion.

Table 10

Only the information provided on the 12 falling clock edges after

the CS falling edge and the initial four write address bits is loaded

state for the four bits RD3 to RD0 when using the control register

to select the power-down modes and gain setting, or when initia-

lizing a calibration. The RD bits should also be set to a logic low

The power-up status of all bits is 0, and the MSB denotes the first

bit in the data stream. The bit functions are outlined in Table 9.

Table 8. Control Register Bits

MSB

LSB

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RD3

RD2

RD1

RD0

CAL

PD2

PD1

PD0

G3

G2

G1

G0

Table 9. Control Register Bit Function Descriptions

Bits

Mnemonic

Comment

11 to 8

RD3 to RD0

Register address bits. These bits select which register the subsequent read is from. See Table 11.

7

CAL

Setting this bit high initiates an internal offset calibration. When the calibration is completed, this pin can be reset low,

and the internal offset that is stored in the on-chip offset registers is automatically removed from the ADCs results.

6 to 4

PD2 to PD0

Power-down bits. These bits select which power-down mode is programmed. See Table 7.

3 to 0

G3 to G0

Gain selection bits. These bits select which gain setting is used on the front-end PGA. See Table 6.

Table 10. Write Address Bits

WR3

WR2

WR1

WR0

Read Register Addressed

0

0

0

1

Control register

CS

SCLK

10

14

16

THREE-STATE

11

12

13

17

THREE-

STATE

15

DB12

DB13

18

20

19

32

33

DB0

THREE-STATE

WR1

WR0

RD3

RD2

RD1

RD0

CAL

PD2

PD1

PD0

G3

G2

G1

G0

WR2

WR3

9

8

7

6

5

4

3

2

1

Figure 30. Timing Diagram for a Write Operation to the Control Register