ADE7569 datasheet(21/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 21 of 148

Pin No.

Mnemonic

Description

49, 50

VP, VN

Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum

differential level of

±500mV for specified operation. This channel also has an internal PGA.

This pin is used as an input for emulation. When held high, this input enables the device to fetch code

from internal program memory locations.The ADE75xx/ADE71xx does not support external code

memory. This pin should not be left floating.

52, 53

IP, IN

Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum

differential level of

±500mV for specified operation. This channel also has an internal PGA.

AGND

This pin provides the ground reference for the analog circuitry

IPB

Analog Inputs for second Current Channel. This input is fully differential with a maximum differential

level of

±500mVrefered to IN for specified operation. This channel also has an internal PGA.

RESET

Reset input, Active low

REFIN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 8% and a typical temperature coefficient of 50 ppm/°C maximum

VBAT

3.3V Power supply input from Battery. This pin is connected internally to VDD when the Battery is

selected as the power supply for the ADE75xx/ADE71xx.

VINTA

This pin provides access to the on-chip 2.5V analog LDO. No external active circuitry should be

connected to this pin. This pin should be decoupled with a 10

μF capacitor in parallel with a ceramic

100nF capacitor.

VDD

3.3V Power supply input from regulator. This pin is connected internally to VDD when the regulator is

selected as the power supply for the ADE75xx/ADE71xx. This pin should be decoupled with a 10

μF

capacitor in parallel with a ceramic 100nF capacitor.

VSWOUT

3.3V Power supply output from ADE75xx/ADE71xx. This pin provides the supply voltage for the LDOs

and internal cicuitry of the ADE75xx/ADE71xx. This pin should be decoupled with a 10

μF capacitor in

parallel with a ceramic 100nF capacitor.

VINTD

This pin provides access to the on-chip 2.5V digital LDO. No external active circuitry should be

connected to this pin. This pin should be decoupled with a 10

μF capacitor in parallel with a ceramic

100nF capacitor.

DGND

This pin provides the ground reference for the digital circuitry

VDCIN

Analog input for dc voltage monitoring. The maximum input voltage on this pin is xxxmV with respect

to AGND. This pin is used to monitor the pre-regulated dc voltage. A dedicated ADC measures the

voltage on this pin—see the External Voltage Measurement section.

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