All trademarks mentioned in this document

http://www.DigitalCoreDesign.com

are trademarks of their respective owners.

http://www.dcd.pl

Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restriction

except One Year license where time of use is

limited to 12 months.

○

VHDL, Verilog source code called HDL

Source

○

Encrypted, or plain text EDIF called Netlist

○

Encrypted Netlist only

○

HDL Source

○

Netlist

○

HDL Source to Netlist

○

Single Design to Unlimited Designs

DESIGN FEATURES

♦

PROGRAM MEMORY:

The DP8051CPU soft core is dedicated

for operation with Internal and External Pro-

gram Memory. Internal Program Memory

can be implemented as:

0000h

÷ (ROM

External Program Memory can be im-

plemented as ROM or RAM located in ad-

♦

INTERNAL DATA MEMORY:

The DP8051CPU can address Internal

Data Memory of up to 256 bytes The Inter-

nal Data Memory can be implemented as

Single-Port synchronous RAM.

♦

EXTERNAL DATA MEMORY:

The DP8051CPU soft core can address

up to 16 MB of External Data Memory. Ex-

tra DPX (Data Pointer eXtended) register is

used for segments swapping.

♦

USER

Up to 104 External (user) Special Func-

tion Registers (ESFRs) may be added to

the DP8051CPU design. ESFRs are mem-

ory mapped into Direct Memory between

addresses 80 hex and FF hex in the same

manner as core SFRs and may occupy any

address that is not occupied by a core

SFR.

♦

WAIT STATES SUPPORT:

The DP8051CPU soft core is dedicated

for operation with wide range of Program

and Data memories. Slow Program and Ex-

ternal Data memory may assert a memory

Wait signal to hold up CPU activity.