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prgdatao[7:0]

output Data bus for internal program memory

prgramwr

output Internal program memory write

xaddr[23:0]

output Address bus for external memories

xdatao[7:0]

output Data bus for external memories

xdataz

output Turn xdata bus into ‘Z’ state

xprgrd

output External program memory read

xprgwr

output External program memory write

xramrd

output External data memory read

xramwr

output External data memory write

ramaddr[7:0]

output Internal Data Memory address bus

ramdatao[7:0]

output Data bus for internal data memory

ramoe

output Internal data memory output enable

ramwe

output Internal data memory write enable

sfraddr[6:0]

output Address bus for user SFR’s

sfrdatao[7:0]

output Data bus for user SFR’s

sfroe

output User SFR’s read enable

sfrwe

output User SFR’s write enable

docddatao

output DoCD™ data output

docdclk

output DoCD™ clock line

pmm

output Power management mode indicator

stop

output Stop mode indicator

UNITS SUMMARY

ALU

– Arithmetic Logic Unit performs the

arithmetic and logic operations during execu-

tion of an instruction. It contains accumulator

(ACC), Program Status Word (PSW), (B) regis-

ters and related logic such as arithmetic unit,

logic unit, multiplier and divider.

Opcode Decoder

– Performs an instruction

opcode decoding and the control functions for

all other blocks.

Control Unit

– Performs the core synchroniza-

tion and data flow control. This module is di-

rectly connected to Opcode Decoder and

manages execution of all microcontroller tasks.

Program Memory Interface

– Contains Pro-

gram Counter (PC) and related logic. It per-

forms the instructions code fetching. Program

Memory can be also written. This feature al-

lows usage of a small boot loader loading new

program into ROM, RAM, EPROM or FLASH

EEPROM storage via UART, SPI, I2C or

DoCD™ module.

External Memory Interface

- Contains mem-

ory access related registers such as Data

Page High (DPH), Data Page Low (DPL) and

Data Pointer eXtended (DPX) registers. It per-

forms the external Program and Data Memory

addressing and data transfers. Program fetch

cycle length can be programmed by user. This

feature is called Program Memory Wait States,

and allows core to work with different speed

program memories.

Internal Data Memory Interface

– Internal

Data Memory interface controls access into the

internal 256 bytes memory. It contains 8-bit

Stack Pointer (SP) register and related logic.

User SFRs Interface

– Special Function Reg-

isters interface controls access to the special

registers. It contains standard and used de-

fined registers and related logic. User defined

external devices can be quickly accessed

(read, written, modified) using all direct ad-

dressing mode instructions.

Interrupt Controller

– Interrupt control module

is responsible for the interrupt manage system

for the external and internal interrupt sources.

It contains interrupt related registers such as

Interrupt Enable (IE), Interrupt Priority (IP) and

(TCON) registers.

Power Management Unit

– Block contains

advanced power saving mechanisms with

switchback feature, allowing external clock

control logic to stop clocking (Stop mode) or

run core in lower clock frequency (Power Man-

agement Mode) to significantly reduce power

consumption.

Switchback

feature

allows

UARTs, and interrupts to be processed in full

speed mode if enabled. It is very desired when

microcontroller is planned to use in portable

and power critical applications.

DoCD™ Debug Unit

– it’s a real-time hard-

ware debugger provides debugging capability

of a whole SoC system. In contrast to other on-

chip debuggers DoCD™ provides non-intrusive

debugging of running application. It can halt,

run, step into or skip an instruction, read/write

any contents of microcontroller including all

registers, internal, external, program memo-

ries, all SFRs including user defined peripher-

als. Hardware breakpoints can be set and con-

trolled on program memory, internal and exter-

nal data memories, as well as on SFRs. Hard-

ware breakpoint is executed if any write/read

occurred at particular address with certain data

pattern or without pattern. The DoCD™ system

includes three-wire interface and complete set

of tools to communicate and work with core in

real time debugging. It is built as scalable unit

and some features can be turned off to save

silicon and reduce power consumption. A spe-

cial care on power consumption has been

taken, and when debugger is not used it is