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automatically switched in power save mode.

Finally whole debugger is turned off when de-

bug option is no longer used.

PROGRAM CODE SPACE

IMPLEMENTATIO N

The figure below shows an example Pro-

gram Memory space implementation in sys-

tems with DP8051CPU Microcontroller core.

The On-chip Program Memory located in ad-

dress space between 0kB and 1kB is typically

used for BOOT code with system initialization

functions. This part of the code is typically im-

plemented as ROM. The On-chip Program

Memory located in address space between

60kB and 64kB is typically used for timing criti-

cal part of the code e.g. interrupt subroutines,

arithmetic functions etc. This part of the code is

typically implemented as RAM and can be

loaded by the BOOT code during initialization

phase from Off-chip memory or through RS232

interface from external device. From the two

mentioned above spaces program code is

executed without wait-states and can achieve

a top performance up to 200 million instruc-

tions per second (many instructions executed

in one clock cycle). The Off-chip Program

Memory located in address space between

1kB and 60kB is typically used for main code

and constants. This part of the code is usually

implemented as ROM, SRAM or FLASH de-

vice. Because of relatively long access time

the program code executed from mentioned

above devices must be fetched with additional

Wait-States. Number of required Wait-States

depends

on

memory

access

time

and

DP8051CPU clock frequency. In most cases

the proper number of Wait-States cycles is

between 2-5. The READY pin can be also dy-

namically modulated e.g. by SDRAM control-

ler.

0x0400

0xF000

On-chip Memory

(implemented as ROM)

On chip Memory

(implemented as RAM)

Off chip Memory

(implemented as ROM,

SRAM or FLASH)

0x0000

0xFFFF

The figure below shows a typical Program

Memories

connections

in

system

with

DP8051CPU Microcontroller core.

10

12

8

prgaddr

On-chip Memory

(implemented as ROM)

0 Wait-State access

On-

chip Memory

(implemented as RAM)

0 Wait-State access

prgromdata

i

prgramdatai

prgdatao

prgramwr

8

xdatai

8

8

xdatao

xaddr

16

xprgrd

xprgwr

Off-chip Memory

(implemented as

FLASH, or SRAM)

eg. 2-5 Wait-State

access

ASIC or FPGA

chip

ready

Wait-States

manager

DP8051CPU

The described above implementation should be

treated as an example. All Program Memory

spaces are fully configurable. For timing-critical

applications whole program code can be imple-

mented as on-chip ROM and (or) RAM and

executed without Wait-States, but for some

other applications whole program code can be

implemented as off-chip ROM or FLASH and

executed with required number Wait-State cy-

cles.