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are trademarks of their respective owners.

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PERFORMANCE

The following tables give a survey about the

Core area and performance in ASICs Devices

(CPU features and peripherals have been in-

cluded):

Device

Optimization

0.25u typical

area

100 MHz

0.25u typical

speed

250 MHz

Core performance in ASIC devices

For a user the most important is application

speed improvement. The most commonly used

arithmetic functions and theirs improvement

are shown in table below. Improvement was

computed as {80C51 clock periods} divided by

{DP8051CPU clock periods} required to exe-

cute an identical function. More details are

available in core documentation.

Function

Improvement

8-bit addition (immediate data)

9,00

8-bit addition (direct addressing)

9,00

8-bit addition (indirect addressing)

9,00

8-bit addition (register addressing)

12,00

8-bit subtraction (immediate data)

9,00

8-bit subtraction (direct addressing)

9,00

8-bit subtraction (indirect addressing)

9,00

8-bit subtraction (register addressing)

12,00

8-bit multiplication

16,00

8-bit division

9,60

16-bit addition

12,00

16-bit subtraction

12,00

16-bit multiplication

13,60

32-bit addition

12,00

32-bit subtraction

12,00

32-bit multiplication

12,60

Average speed improvement:

11,12

Dhrystone Benchmark Version 2.1 was used to

measure Core performance. The following ta-

ble gives a survey about the DP8051CPU per-

formance in terms of Dhrystone/sec and VAX

MIPS rating.

Device

Target

Clock

frequency

Dhry/sec

(VAX MIPS)

80C51

-

12 MHz

268 (0.153)

80C310

-

33 MHz

1550 (0.882)

DP8051

0.25u

250 MHz 43700 (24.872)

Core performance in terms of Dhrystones

268

1550

43700

0

5000

10000

15000

20000

25000

30000

35000

40000

45000

80C51 (12MHz)

80C310 (33MHz)

DP8051CPU (250MHz)

Area utilized by the each unit of DP8051CPU

core in vendor specific technologies is summa-

rized in table below.

Area

Component

[Gates]

[FFs]

CPU*

5900

285

Interrupt Controller

350

40

Power Management Unit

50

5

Total area

6300

330

*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &

Internal & External Memory Interfaces, User SFRs Interface

Core components area utilization