T80C5112-RKSCL datasheet(66/97 Pages) ATMEL

66 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.

A high-priority interrupt canÕt be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level

is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence

determines which request is serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

Table 40. Priority bit level values

IPH.x

IP.x

Interrupt Level Priority

0 (Lowest)

3 (Highest)

Table 41. Address vectors

Interrupt Name

Interrupt Address

Vector

Priority Number

external interrupt (INT0)

0003h

Timer0 (TF0)

000Bh

external interrupt (INT1)

0013h

Timer1 (TF1)

001Bh

PCA (CF or CCFn)

0033h

UART (RI or TI)

0023h

SPI

004Bh

ADC

0043h

T80C5112-RKSCL 数据表(PDF) 66 Page - ATMEL Corporation

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