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T80C5112-RKSIL 数据表(PDF) 72 Page - ATMEL Corporation |
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T80C5112-RKSIL 数据表(HTML) 72 Page - ATMEL Corporation |
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72 / 97 page  72 Rev. B - November 10, 2000 Preliminary T80C5112 Reset Value = XXXX X00Xb Not bit addressable Table 47. IPH1 Register IPH1 - Interrupt Priority High Register 1 (B3h) 7 6 5 4 3 2 1 0 - - - - - PSPIH PADCH - Bit Number Bit Mnemonic Description 7 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 PSPIH SPI Interrupt Priority level most significant bit PSPIH PSPI Priority level 0 0Lowest 01 10 1 1Highest 1 PADCH ADC Interrupt Priority level most significant bit PADCH PADC Priority level 0 0Lowest 01 10 1 1Highest 0 - Reserved The value read from this bit is indeterminate. Do not set this bit. |
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