| 数据搜索系统,热门电子元器件搜索 |
|
T80C5112-RKSIL 数据表(PDF) 59 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
T80C5112-RKSIL 数据表(HTML) 59 Page - ATMEL Corporation |
|
59 / 97 page ![]() Rev. B - November 10, 2000 59 Preliminary T80C5112 14. Analog-to-Digital Converter (ADC) 14.1. Introduction This section describes the on-chip 10 bit analog-to-digital converter of the T80C5112. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit- cascaded potentiometric ADC. Three kind of conversion are available: · Standard conversion (7-8 bits). · Precision conversion (8-9 bits). · Accurate conversion (10 bits). For the precision conversion, set bits PSIDLE and ADSST in ADCON register to start the conversion. The chip is in a idle mode, the CPU doesnÕt run but the peripherals are always running. This mode allows digital noise to be lower, to ensure precise conversion. For the accurate conversion, set bits QUIETM and ADSST in ADCON register to start the conversion. The chip is in a pseudo-idle mode, the AD is the only peripheral running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For these modes it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip. If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended. 14.2. Features · 8 channels with multiplexed inputs · 10-bit cascaded potentiometric ADC · Conversion time 40 micro-seconds · Zero Error (offset) +/- 2 LSB max · External Positive Reference Voltage Range 2.4 to Vcc · Internal Positive Reference Voltage 2.4 Volt. If Vref is used as output, the load must be higher than 18 kOhm. · ADCIN Range 0 to Vcc · Integral non-linearity typical 1 LSB, max. 2 LSB · Differential non-linearity typical 0.5 LSB, max. 1 LSB · Conversion Complete Flag or Conversion Complete Interrupt · Selected ADC Clock 14.3. ADC I/O Functions AINx are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel pin will be used as ADCIN. The remaining ADC channels pins can be used as general purpose I/O or as the alternate function that is available. Writes to the port register which arenÕt selected by the ADCF will not have any effect. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |