T80C5112-RKSIL datasheet(32/97 Pages) ATMEL

32 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

Figure 12. UART Timings in Modes 2 and 3

11.2. Automatic Address Recognition

The automatic address recognition feature is enabled for each UART when the multiprocessor communication

feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by

allowing the serial port to examine the address of each incoming command frame. Only when the serial port

recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that

the CPU is not interrupted by command frames addressed to other devices.

If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit

takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the

deviceÕs address and is terminated by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and a broadcast address.

NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON

11.2.1. Given Address

Each UART has an individual address that is specified in SADDR register; the SADEN register is a mask byte

that contains donÕt-care bits (defined by zeros) to form the deviceÕs given address. The donÕt-care bits provide the

flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b

For example:

SADDR

0101 0110b

SADEN

1111 1100b

Given

0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:

SADDR

1111 0001b

SADEN

1111 1010b

Given

1111 0X0Xb

Slave B:

SADDR

1111 0011b

SADEN

1111 1001b

Given

1111 0XX1b

Slave C:

SADDR

1111 0010b

SADEN

1111 1101b

Given

1111 00X1b

SMOD0=0

Data byte

Ninth

bit

Stop

bit

Start

bit

RXD

SMOD0=1

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