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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STE2002 数据表(PDF) 23 Page - STMicroelectronics |
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STE2002 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 51 page  23/51 STE2002 If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte at the next SCLK positive edge. A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal registers are cleared. If SCE is low after the positive edge of RES, the serial interface is ready to receive data. Throughout SOUT can be read only the driver I2C slave address. The Command sequence that allows to read I2C slave address is reported in Fig. 34 & 35. SOUT is in High impedance in steady state and during data write. It is possible to short circuit DOUT and SDIN and read I2C address without any additional lines. Figure 32. Serial bus protocol - one byte transmission Figure 33. Serial bus protocol - several byte transmission Figure 34. Serial bus protocol - several byte transmission MSB LSB D/C SCE SDIN SCLK D00IN1159 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 D/C SCE SDIN SCLK D00IN1160 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Don't Care DB7 DB6 DB5 D/C SCE SDIN SCLK D00IN1160 High-Z DB1 DB0 SOUT High-Z Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Command Write I2C Address Read DB7 DB6 DB5 DB4 DB3 DB2 |
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