STE2002 datasheet(43/51 Pages) STMICROELECTRONICS

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STE2002

Figure 52. Serial interface Timing

Notes: 1.

2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with

an input voltage swing of VSS to VDD

3. Cb is the capacitive load for each bus line.

4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated

5. CVLCD is the filtering Capacitor on VLCDOUT

6. Trise and Tfall (30%-70%) = 10 ns

ELECTRICAL CHARACTERISTICS (continued)

AC OPERATION

(VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11V; Tamb =-40 to 85°C; unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SERIAL INTERFACE

TCYC

Clock Cycle SCLK

VDD1 = 1.7V; Write; note 2, 6

150

TPWH1

SCLK pulse width HIGH

TPWL1

SCLK Pulse width LOW

TS2

SCE setup time

TH2

SCE hold time

TPWH2

SCE minimum high time

TS3

SD/C setup time

TH3

SD/C hold time

TS4

SDIN setup time

TH4

SDIN hold time

TS5

SOUT Access Time

100

TH5

SOUT Disable Time vs. SCLK

100

TH6

SOUT Disable Time vs. SCE

100

D/C

tS2

tS3

tS4

tH2

tPWH2

SDIN

SCLK

tH3

tH4

tPWL1

tWH1

tS2

tCYC

SOUT

tS5

tH5

tH6

LR0001

fra m e

osc

960

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