STE2002 datasheet(39/51 Pages) STMICROELECTRONICS

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STE2002

Notes: 1. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load.

2. Internal clock

3. When fsclk = 0 there is no interface clock.

4. Power-down mode. During power-down all static currents are switched-off.

5. f external VLCD, the display load current is not transmitted to IDD

6. Tolerance depends on the temperature; (typically zero at Tamb = 27°C), maximum tolerance values are measured at the temper-

ature range limit.

7. For TC0 to TC7

8. Data Byte Writing Mode

9.VDD1 ≤ VDD2

Logic Inputs

VIL

Logic LOW voltage level

VSS

0.3VDD1

VIH

Logic HIGH Voltage Level

0.7VDD1

VDD2

Iin

Input Current

Vin = VSS1 or VDD1

-1

µA

Logic Inputs/Outputs

VIL

Logic LOW voltage level

VSS

0.3VDD1

VIH

Logic HIGH Voltage Level

0.7VDD1

VDD1

+0.5V

Column and Row Driver

Rrow

ROW Output Resistance

VLCD = 10V;

kohm

Rcol

Column Output resistance

VLCD = 10V;

10K

kohm

Vcol

Column Bias voltage accuracy

No load

-50

+50

Vrow

Row Bias voltage accuracy

-50

+50

LCD Supply Voltage

VLCD

LCD Supply Voltage accuracy;

Internally generated

VDD = 2.8V; VLCD = 10V; fsclk=0;

Tamb=25°C;

no display load; note 2, 3, 6 & 7;

VOP = 61h, PRS = 2hex

-1.5

1.5

TC0

Temperature coefficient

-0.0·10-3

1/°C

TC1

-0.35·10-3

1/°C

TC2

-0.7·10-3

1/°C

TC3

-1.05·10-3

1/°C

TC4

-1.4 ·10-3

1/°C

TC5

-1.75·10-3

1/°C

TC6

-2.1·10-3

1/°C

TC7

-2.3·10-3

1/°C

ELECTRICAL CHARACTERISTICS (continued)

DC OPERATION

(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11 V; Tamb =-40 to 85°C; unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

STE2002 数据表(PDF) 39 Page - STMicroelectronics

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